1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a method and apparatus for driving a liquid crystal display panel can minimize the deterioration of picture quality caused by variations in the gate low voltage.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls the light transmittance of a liquid crystal having a positive or negative dielectric anisotropy by using an electric field. To this end, the LCD includes a liquid crystal display panel for displaying a picture, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel arranges liquid crystal cells in a matrix to control the light transmittance in accordance with pixel signals, thereby displaying a picture.
The driving circuit includes a gate driver for driving gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, and a power supply for supplying power signals required for driving the liquid crystal display panel and the driving circuit.
The data driver and the gate driver are separated into a multiple drive integrated circuits (IC's). Each of the integrated drive IC's is mounted in an opened IC area of a tape carrier package (TCP) or in a base film of the TCP by a chip-on-film (COF) system, to thereby be connected to the liquid crystal display panel by a tape automated bonding (TAB) system. Alternatively, the drive IC may be directly mounted onto the liquid crystal display panel by using a chip-on-glass (COG) system. The timing controller and the power supply are mounted onto a main printed circuit board (PCB).
The drive IC's connected to the liquid crystal display panel by the TAB system are connected, via the TCP, a sub-FCB (i.e., a gate PCB and a data PCB) and a flexible printed circuit (FPC), to the timing controller and the power supply on the main PCB.
The drive IC's mounted onto the liquid crystal display panel by the COG system are connected, via line-on-glass (LOG) type signal lines provided at the FPC and the liquid crystal display panel, to the timing controller and the power supply on the main PCB.
When the drive IC's are connected, via the TCP, to the liquid crystal display panel, the LCD adopts the LOG-type signal lines to reduce the number of PCB's to thereby have a thinner width. Particularly, the gate PCB (which delivers a relatively small number of signals) is removed, and a multiplicity of signal lines for applying gate control signals and power signals to the gate drive IC's are provided on the LOG-type liquid crystal display panel. Thus, the gate drive IC's mounted in the TCP receives the control signals from the timing controller and the power signals from the power supply by way of the main PCB, FPC, the data PCB, the data TCP, the LOG-type signal lines and the gate TCP in turn. In this case, the gate control signals and the gate power signals applied to the gate drive IC's are distorted by line resistances of the LOG-type signal lines, and this distortion results in quality deterioration of the picture displayed on the liquid crystal display panel.
More specifically, as shown in FIG. 1, a LOG-type LCD removed with the gate PCB includes a data PCB 16, a data TCP 12 mounted with a data driving IC 14 and connected between the data PCB 16 and a liquid crystal display panel 6, and a gate TCP 8 mounted with a gate driving IC 10 and connected to the liquid crystal display panel 6.
The liquid crystal display panel 6 has a thin film transistor array substrate 2 and a color filter array substrate 4 joined to each other and having a liquid crystal therebetween. Such a liquid crystal display panel 6 includes liquid crystal cells defined at intersections between gate lines GL and data lines DL, each of which has a thin film transistor as a switching device. The thin film transistor applies a pixel signals from the data line DL to the liquid crystal cell in response to a scanning signal from the gate line GL.
The data drive IC 14 connects, via the data TCP 12 and a data pad of the liquid crystal display panel, to the data line DL. The data drive IC 14 converts digital pixel data into an analog pixel signal and applies it to the data line DL. To this end, the data drive IC 14 receives a data control signal and a pixel data from a timing controller (not shown) and a power signal from a power supply (not shown) by way of the data PCB 16.
The gate drive IC 10 connects, via the gate TCP 8 and a gate pad of the liquid crystal display panel 6, to the gate line GL. The gate drive IC 10 sequentially applies a scanning signal having a gate high voltage VGH to the gate lines GL. Further, the gate drive IC 10 applies a gate low voltage VGL to the gate lines GL in the remaining interval (excluding the time interval when the gate high voltage VGH has been supplied).
To this end, the gate control signals from the timing controller and the power signals from the power supply are applied, via the data PCB 16, to the data TCP 12. The gate control signals and the power signals applied via the data TCP 12 are applied (via a LOG-type signal line group 20 provided at the edge area of the thin film transistor array substrate 2) to the gate TCP 8. The gate control signals and the power signals applied to the gate TCP 8 are inputted, via input terminals of the gate drive IC 10, within the gate drive IC 10. Further, the gate control signals and the power signals are outputted via output terminals of the gate drive IC 10, and are applied, via the gate TCP 8 and the LOG-type signal line group 20, to the gate drive IC 10 mounted in the next gate TCP 8.
The LOG-type signal line group 20 is typically contains signal lines for supplying direct current driving voltages from the power supply, such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND and a base driving voltage VCC. The LOG-type signal line group 20 also supplies gate control signals from the timing controller, such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE.
The LOG-type signal line group 20 is formed in a fine pattern from the same gate metal layer as the gate lines at a specific pad area of the thin film transistor array substrate 2. Thus, the LOG-type signal line group 20 has a larger line resistance than the signal lines on the existing gate PCB. This line resistance distorts gate control signals (i.e., GSP, GSC and GOE) and power signals (i.e., VGH, VGL, VCC, GND and VCOM), thereby causing picture quality deterioration phenomena such as a horizontal line (i.e., gate dim) 32, cross talk in the dot pattern and a greenish hue, etc. as shown in FIG. 2.
FIG. 2 depicts a view for explaining a horizontal line phenomenon caused by the LOG-type signal line group 20.
Referring to FIG. 2, the LOG-type signal line group 20 contains a first LOG-type signal line group LOG1 connected to an input terminal of a first gate TCP 8. A second LOG-type signal line group LOG2 connects to an input terminal of a second gate TCP 9. A third LOG-type signal line group LOG3 connects to an input terminal of a third gate TCP 13. The first to third LOG-type signal line groups LOG1 to LOG3 have line resistances aΩ, bΩ and cΩ proportional to the line length thereof, respectively. The first to third LOG-type signal line groups LOG1 to LOG3 are also connected, via the gate TCP's 8, 9 and 13, to each other in series.
The first gate drive IC 10 is thus supplied with gate control signals GSP, GSC and GOE and power signals VGH, VGL, VCC, GND and VCOM voltage-dropped by the line resistance aΩ of the first LOG-type signal line group LOG1. The second gate drive IC 11 is thus supplied with those voltage-dropped by the line resistances aΩ+bΩ of the first and second LOG-type signal line groups LOG1 and LOG2, and the third gate drive IC 15 is supplied with those voltage-dropped by the line resistances aΩ+bΩ+cΩ of the first to third LOG-type signal line groups LOG1 to LOG3.
A voltage difference is accordingly generated among gate signals VG1 to VG3 applied to the gate lines of first to third horizontal blocks A to C driven with different gate drive IC's 10, 11 and 15, thereby causing horizontal lines 32 among the first to third horizontal line blocks A to C.
FIG. 3 shows a gate signal waveform applied to a certain gate line GLi included in the liquid crystal display panel shown in FIG. 1.
The certain gate line GLi must maintain a gate low voltage VGL except for a horizontal period Hi when it arrives at a sequence to be scanned and thus is supplied with a gate high voltage VGH. However, the gate low voltage VGL supplied to the gate line GLi (owing to a parasitic capacitance between the gate line GLi and the data line DL crossing each other while having a gate insulating film therebetween) is swung in response to a pixel signal applied to the data line DL, and becomes unstable. For example, the gate low voltage VGL is alternately swung towards positive polarity and negative polarity every horizontal period in accordance with an average value of pixel signals applied to one horizontal line, while alternating positive and negative polarities in response to a dot inversion system. Such a swing phenomenon of the gate low voltage VGL is generated similarly at other gate lines to which the gate low voltage VGL is commonly applied via the LOG-type signal lines LOG1, LOG2 and LOG3 of the gate drive IC's 10, 11 and 15, respectively.
The unstable gate low voltage VGL caused by the parasitic capacitance can be stabilized more rapidly as the load amount (i.e., a capacitor and a resistor) applied thereto becomes smaller. However, as the gate low voltage VGL is commonly applied to other gate lines GL, the unstable gate low voltage VGL fails to rapidly stabilize because the value of the parasitic capacitance associated with the gate low voltage VGL increases, and the LOG resistance value becomes large.
Accordingly, the unstable gate low voltage VGL varies the pixel voltage via a storage capacitor Cst provided between the pixel electrode and the pre-stage gate line. As a result, when a specific dot pattern is displayed by a dot inversion system, one encounters the problem of a greenish phenomenon in which a green (G) pixel having the polarity opposite to adjacent red (R) and blue (B) pixels is observed at a relatively large brightness to cause deterioration of the picture quality. Furthermore, when a window pattern is displayed by a dot inversion system, one observes a problem of horizontal cross talk in which a peripheral area adjacent to the window pattern in a horizontal direction is observed at a relatively large brightness, thereby causing deterioration of the picture quality.